Electrostatic Discharge (ESD) protection is a desirable feature for integrated circuits. With a low breakdown voltage of transistors in submicron processes it is important to protect power supply pins and pads from ESD damage, especially on smaller integrated circuits where there is no high capacitance available to absorb current from a discharge. Power clamp circuits, such as a shunt circuit, may be used to provide ESD protection. A shunt circuit responds to a rapid rise of voltage on a power supply line, sometimes referred to as an ESD upset event, by shunting a power supply line to ground. Alternatively, protection diodes coupled to the positive and negative power supplies on an integrated circuit may be used for ESD protection, as desired.
It is possible to distinguish between an ESD upset event and a normal application of power by a difference in rise time. For instance, in a state of the art integrated circuit a rise time on a power supply line may be on the order of nanoseconds (ns) for an ESD upset event, whereas a rise time during regular application of power to the supply line may be on the order of microseconds (μs). Therefore, there may be an order of magnitude difference between an ESD upset event and regular application rise time.
In some instances during normal operation when several outputs switch simultaneously, it is possible that a voltage drop due to noise, such as an IR or RLC voltage drop, on a power supply line can be substantially similar to an ESD upset event rise time range triggering erroneous or false protection. A false trigger during normal operation is undesirable and may damage the integrated circuit or the system in which it is used.